1. Field of the Invention
The present invention relates to a semiconductor device and a method of connecting the semiconductor device, and more particularly to a connecting method for mounting a semiconductor device on a wiring board which configures a system, a connecting method for mounting semiconductor elements (hereinafter referred to as the semiconductor chips), which also configure the semiconductor device, on the wiring board configuring the semiconductor device, and a connecting method for semiconductor chips which configure the semiconductor device.
2. Description of the Related Art
A semiconductor device is configured by mounting one or plural semiconductor elements on a mounting substrate such as a wiring board. In recent years, flip-chip mounting is employed to bond connection electrodes such as projecting electrodes (also called as bumps) formed on the surface of a semiconductor chip, to wires or electrodes formed on a wiring board, thereby mounting the semiconductor elements on the mounting substrate. It is a general method that the solder bumps of the semiconductor chip are aligned with the electrodes of the wiring board and heated to melt so as to bond and fix the solder bumps with the electrodes. The bumps on the semiconductor chip are configured by forming openings in an insulating film which is coated to protect the electrode pads of Al or Cu of the semiconductor chip, forming a barrier metal such as Ti/Ni, Ti/Ni/Pd, Cr/Cu or the like thereon, and further forming bumps of Sn/Pb solder or the like thereon. The semiconductor device having such a flip-chip mounting structure may protect a gap between the semiconductor chip and the wiring board by an underfill resin or protect the wiring board and the semiconductor chip as a whole by coating a mold resin or the like.
FIG. 11A and FIG. 11B show examples of a prior art method of connecting a semiconductor chip to a wiring board. FIG. 11A shows a conventional semiconductor device which has the semiconductor chip flip-chip mounted on the wiring board. A protective insulating film 108 such as a silicon oxide film is applied onto the main surface of a semiconductor substrate 101. On the main surface on which the protective insulating film 108 is formed, electrode pads 104 of Al or the like which are electrically connected to an inside integrated circuit, barrier metal layers 105 which are on the electrode pads 104 and extend to reach the protective insulating film 108 over the electrode pads 104, and bumps 103 formed of solder mainly consisting of Pb, Sn and the like and formed on the barrier metal layers 105 are formed (FIG. 11A). Meanwhile, a wiring board 102 on which the semiconductor substrate 101 is mounted has wiring patterns of Cu or the like and electrode pads 106 partly forming the wiring patterns on its main surface. Barrier metal layers 107 of Ni/Au, Pb—Sn or the like are formed on the electrode pads 106. The plural bumps 103 on the semiconductor substrate 101 are electrically connected to the electrode pads 106 which are formed on the surface of the wiring board 102, and the semiconductor substrate 101 is mounted on the wiring board 102. For the bumps 103, gold may be used other than the solder. As the solder material, Pb—Sn, Sn—Ag, Sn—Ag—Cu or the like is generally used. For the mounting substrate 102, a glass epoxy substrate, a ceramic substrate, a flexible substrate or the like is used.
A conventional method of producing a semiconductor device using conductive particles for the connection structure is described in, for example, Japanese Patent Laid-Open Application No. HEI 7-211721. The formation of bumps by blowing fine metal particles is described in, for example, Japanese Patent No. 3283977. A method of blowing fine metal particles onto connections is described in, for example, Japanese Patent Publication No. HEI 7-114218.
A production of a semiconductor device which has semiconductor chips mounted on a wiring board has a problem of thermal stress at the connecting time. For example, when a glass epoxy substrate is used for the wiring board, Si as a material for the semiconductor chip and the glass epoxy substrate as the wiring board have a large difference in a thermal expansion coefficient, so that solder bumps interposed between them are exposed to stresses from both of them when they are cooled from the temperature at the connecting time to room temperature, and the bumps and an insulating film below them have a possibility of breakage (see FIG. 11C). This problem becomes obvious when the bumps themselves become to be hardened by omitting Pb from Pb—Sn solder for the protection of environment, when a pitch of the bumps becomes microscopic, or when a fragile material such as a low dielectric constant film is used for the insulating layer of the semiconductor element. Therefore, the temperature at the time of connection is desired to be 100° C. or below at which a stress is small.
As a connection method at a low temperature, the prior art methods proposed and developed include a method using a low-melting metal, a method using an anisotropic conductive film (ACF), a method connecting in a high vacuum and the like. But, where a material for the low-melting metal is selected to lower the melting point to 100° C. or below, the cost of the metal itself increases, and oxidation causes degradation in reliability of connection, difficulty in processing and the like, so that the application of such a metal to general parts is hard to realize. The connection method using the ACF holds a resin film containing conductive particles between the electrode surface of the semiconductor chip and the wiring pattern surface of the wiring board, heats and pressurizes them to effect the electrical connection. This method has problems that the device, chips, bumps and the like are highly required to be even, bringing about a cost rise and a mechanical damage to the semiconductor element when pressurized. The connection in a high vacuum causes technical and cost problems such as surface cleanliness, necessity of high-vacuum equipment and the like in addition to the problem of the evenness.
Regardless of which method is used, if a semiconductor chip once connected to the wiring board by the burn-in or the test thereafter is defective, it is hard to remove the defective semiconductor chip and to mount another semiconductor chip in the same position. Therefore, burn-in or test thereafter is generally performed after mounting all the semiconductor chips, in the case of the semiconductor device on which plural semiconductor chips are mounted. If it is found that the semiconductor device has a defective semiconductor chip, it is necessary to change the defective part to another semiconductor chip. But, the prior art connection method is hard to exchange the semiconductor chips after connecting, so that the occurrence of a defective product results in disposal of the wiring board and the semiconductor chips together. Therefore, where plural semiconductor chips are mounted on the wiring board, the mounted other semiconductor chips which are good-quality products and the wiring board must be abandoned as a whole if there is a single defective part, and there was a considerable economic influence.